1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a memory cell, such as that used in a random access memory (RAM) array, having an improved read port. The invention further relates to a complementary metal-oxide semiconducting (CMOS) memory cell having multiple read ports.
2. Description of the Related Art
A conventional computer system typically has a central processing unit (CPU) or processor which is connected to several peripheral devices, including input/output (I/O) devices (such as a display monitor and keyboard) for the user interface, a permanent memory device (such as a hard disk or floppy diskette) for storing the computer's operating system and user programs, a temporary memory device (such as random access memory or RAM) that is used by the processor to carry out program instructions. The computer system may have additional components and peripherals.
There are generally three types of RAM used for computer memory arrays: dynamic RAM, static RAM, and pseudo-static RAM. Dynamic RAM stores data in capacitors, that is, it can hold data for only a few milliseconds, so DRAM is typically refreshed (precharged) using external refresh circuitry. Pseudo-static RAM is like DRAM with internal refresh circuitry. Static RAM is a read-write memory array whose storage cells are typically made up of four or six transistors forming flip-flop elements that indefinitely remain in a given binary state (i.e., 1 or 0, corresponding respectively to high or low voltage states) until the information in the cell is intentionally changed, or the power to the memory circuit is shut off, so this memory does not need to be regularly refreshed. It is only necessary to restore (electrically precharge) the SRAM array after or before each evaluation (read or write operation). RAM arrays can be used for system memory, or for cache arrays.
In a traditional sense amplifier memory array, each memory cell has a pair of outputs (a true line and a complementary line) which constitute the bit line. These lines are connected to a sense amplifier whose output is read by the processor. During an evaluation cycle, a differential signal is developed between the pair. In other words, one of the T/C lines is in a high state, while the other is in a low state. Use of two such outputs and a sense amplifier simplifies evaluation since it does not require that the lines have a precise voltage, but rather only requires that there be a discernable difference between the two lines, i.e., one is higher than the other. It is also necessary to restore (precharge) the differential T/C pair after or before each access of the memory cell, i.e., raise each line to the high state (V.sub.dd).
Memory cells with multiple write and read ports are often used in cache array designs. Each read port has a single bitline which is connected to ground through two n-type metal-oxide semiconducting (NMOS) devices in series. During the precharge phase, the bitline in every read port is precharged to V.sub.dd potential. During the evaluate phase (read), the contents of the accessed memory cell are read by the bitline being discharged to ground through the two NMOS devices if the stored data in the memory cell is a logic "1" (V.sub.dd); if the stored data in the cell is a logic "0" (ground potential) then the bitline would remain at V.sub.dd potential. The gate of one of the two serially-connected NMOS devices is connected to a "wordline" which is used to select an entire memory word (row) in the memory array. The gate of the other NMOS device is connected to the internal storage node of the memory cell. Usually, due to a large capacitive load on the bitline, the performance of the read operation is limited by the size (width) of the two NMOS devices in the read port. Since the size of the array is governed by the memory cell size, the device sizes of the two NMOS devices are usually small (on the order of 2 .mu.m width).
FIG. 1 illustrates a prior art memory cell 10 with three read ports. Read bitlines 12, 14 and 16 are connected to ground through respective pairs of serially-connected NMOS devices 18 and 20, 22 and 24, and 26 and 28. The gates of the upper row of NMOS devices in the read ports (18, 22 and 26) are controlled by read wordlines 30, 32 and 34. The gates of each of the NMOS devices in the lower row in the read ports (20, 24 and 28) are connected to the internal memory storage node 36, i.e., the storage node of a flip-flop formed by inverters 38 and 40. Storage node 36 is also connected to the drain of another NMOS device 42 whose source is connected to ground, and which is controlled by a clear line 44. Writing to the cell is performed using another NMOS device 46 whose source is connected to the input of inverter 40 (the output of inverter 38). The gate of NMOS write device 46 is connected to a write wordline 48, and its drain is connected to the data line 50.
During precharge, bitlines 12, 14 and 16 are charged to V.sub.dd potential and read wordlines 30, 32 and 34 are turned off (at ground potential). During the read operation, PMOS devices holding the bitlines at V.sub.dd (not shown) are turned off. The bitline in each port is discharged to ground if the corresponding wordline is selected (V.sub.dd potential) and the stored data in the memory cell at node 36 is at logic "1" (V.sub.dd potential). If the stored data in the memory cell is a logic "0" (ground potential) then NMOS devices 20, 24 and 28 are turned off and the bitlines remain at V.sub.dd potential.
Various other designs for multiple read port memory cells are known in the art. For example, U.S. Pat. No. 4,592,021 discloses a memory cell which requires a is depletion-type MOS transistor ("T.sub.rd " of FIG. 6 of that patent) to have functional read operation for both data polarities. The cell also uses p-type MOS transistors to discharge the data line to ground potential. This design presents several problems, the first being the requirement of a depletion-type MOS device which complicates the fabrication process. Second, the PMOS device generally takes longer than other (NMOS) devices to discharge since is has a slower conductivity. Finally, the rate that the bitlines are discharged to ground depends upon the number of columns in the array. As the number of columns increases, the number of NMOS devices in the stack increases, which in turn increases the impedance through the NMOS devices in series in the row direction, and results in slower discharge of the bitlines to ground potential. This drawback limits the density of arrays. A further drawback to the construction is that it is efficient only if all of the read ports are used, i.e., no advantage is obtained in using less than all of the read ports and the unused ports represent wasted circuit space. This aspect of that design is particularly bothersome if only a single read port is used. It would, therefore, be desirable to devise a memory cell with multiple read ports which makes more efficient use of space (silicon surface area) so as to decrease the array size, without sacrificing performance. It would be further advantageous if some performance benefit could be achieved by using less than all of the read ports in the memory cell.